The present invention relates to digital multipliers of the "add and shift" type such as may be used in digital filters for telecommunications systems.
In such multipliers multiplication is achieved by performing a number of addition operations using an adder with an accumulator in which the adder output is stored and shifted one bit position for each addition operation. An adder comprises a series of cells, one for each bit in a digital word, each cell having inputs for the addend and the augend and outputs for the sum and carry. A so-called "full adder cell" has in addition a third input to which the carry from the cell of next lesser significance may be applied.
In a known form of multiplier where, say, a parallel coefficient B is to be multiplied by an incoming serial data word C to form the product A=B.times.C in the accumulator, the multiplicand B is applied in parallel to a number of AND gates for the duration of the word C. Each bit of the word C, starting with the least significant bit, is applied to all the AND gates. If a bit of word C is a logic "1" then the multiplicand B is added to the accumulator (if it is a logic "0" nothing is added) and the contents of the accumulator are right shifted before the next bit of word C is applied to the AND gates. This continues until all the bits of word C have been applied to the gates, then the multiplication is complete. The answer A is now in the accumulator and may be extracted as required by various known methods.
Negative numbers can be handled by various known simple modifications. For example, if 2's complement data is used then the most significant bit of the data has a negative weight and for this bit only the multiplicand B is subtracted from instead of added to the accumulator.
In digital filters a digitally encoded sampled signal is filtered by combining together various delayed copies of the signal through suitable weighting coefficients. In general in a digital filter it is thus necessary to form an accumulated product such as: EQU P=(D.sub.1 .times.E.sub.1) + (D.sub.2 .times.E.sub.2) + (D.sub.3 .times.E.sub.3) . . . (D.sub.n .times.E.sub.n),
where D.sub.1, D.sub.2 etc. are filter signal serial data words and E.sub.1, E.sub.2 etc. are the filter tap coefficients. In the simple type of multiplier described above this type of operation can only be accomplished by performing first the multiplication D.sub.1 .times.E.sub.1, storing the result, changing the coefficient E, applied in parallel to the AND gates, performing the next multiplication D.sub.2 .times.E.sub.2, adding the result to the previously stored product D.sub.1 .times.E.sub.1, storing the sum, and repeating this process as many times as required. It is obvious that it would be advantageous to be able to perform all n multiplications simultaneously and produce the product P at the end of one serial data word period rather than to have to wait for n word periods.